The present invention is directed to a GTO-Thyristor having a semiconductor substrate whose cathode-side surface has three levels or planes lying at different heights.
Prior art GTO-Thyristors have:
(a) at least one cathode electrode, each of which contacts a cathode zone, arranged on the first uppermost level; PA1 (b) a pn-junction of the cathode zone that comes to the surface in the second level, the second level lying under the first level; PA1 (c) at least one gate electrode arranged on the third lowest level; and PA1 (d) a first insulating layer covering the pn-junction and a second insulating layer covering at least a part of the first insulating layer and at least a part of the gate electrode. PA1 (e) the first insulating layer being applied exclusively in the second level and in the third level; PA1 (f) the cathode electrode also contacting the emitter zone in the second level and overlapping the first insulating layer; PA1 (g) the gate electrode overlapping that part of the first insulating layer lying in the third level; and PA1 (h) the second insulating layer overlapping the cathode electrode in the second level.
FIG. 2 shows a section through a semiconductor body of such a prior art GTO-Thyristor. The semiconductor substrate 1 contains a p-doped base zone 2 at the cathode-side into which a highly n-doped cathode emitter zone 3 is embedded. The cathode-side surface of the semiconductor body is divided into three levels 4, 5 and 6. A cathode contact 17 that contacts the emitter zone 3 is arranged on the first uppermost level 4. A gate contact 18 lies on the lowest third level 6. This gate contact 18 contacts the base zone 2 via a highly p-doped zone 10. The second level 5 within which the pn-junction comes to the surface between the cathode emitter zone 3 and the base zone 2 lies vertically between the levels 4 and 6. On the first level 4, the cathode electrode 17 overlaps a first insulating layer 21 composed of silicon nitride that extends over all three levels. The insulator level 21 is overlapped by the gate contact 18 on the third level 6. The second insulator layer 22 of, for example, a polyamide, is placed over the gate electrode 18 and over the first insulator layer 22.
The known prior art solution has the disadvantage that the insulation layers 21, 22 extend over all three levels. The edges of the electrodes likewise lie vertically far apart, namely in the first level and in the third level. It is not possible with traditional phototechniques to structure the edges of the layers lying in the first and third level to be edge-sharp. The reason for this is that the depth of field of traditional automatic exposure units is less than the distance between the first level 4 and the third level 6. It is thus often not possible to join the second insulating layer 22 flush to the edge of the cathode electrode 17. Since an overlap is not permitted here, the passivation is incomplete in this region.